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Message
From: John Sheahan<jrsheahan@o...>
Date: Wed Feb 9 22:33:03 CET 2005
Subject: [oc] I2C test bench timing violations?
> As I mentioned, I'm also seeing width violations on the SCL line.
> Apparently the slave_wait signal is holding off the external SCL causing
> it to be too short. It's high for 3.6us which is short of the 4.0us in
> the spec. ftp://hanochnet.org/pub/state_machine_scl_width.jpg shows this.
>
sorry , just deleted Richard's mail by mistake. finger trouble :(
I don't agree that a timing violation caused by the slave giving itself
wait time by holding scl low is something the master has no control over.
Surely having the master start timing the requisite SCL high pulse
after the slave releases the open drain SCL line would be the
appripriate solution?
john
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