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Message
From: Jeff Hanoch<jeff@l...>
Date: Wed Feb 2 04:05:22 CET 2005
Subject: [oc] I2C test bench timing violations?
I'm trying to simulate the I2C controller using the code I just
downloaded from CVS.
I'm getting many timing violations specifically setup on the start
condition (SDA falling to SCL falling is 4.2us instead of 4.7us). Also
getting SCL width errors (3.6us instead of 4.0us). The expected numbers
in the timing checks agree with the published I2C spec.
Has anyone else had problems with the timing of this core? It's going
into an ASIC very quickly and I'm a little concerned.
I've changed the prescaler to run at 85KHz instead of 100KHz and this
seems to fix most of the violations (I'm still getting 1 setup
violation).
Are these "real" issues I need to fix, or are they not an issue with the
I2C parts on the market today?
Any input would be appreciated.
Thanks,
Jeff
P.S. Here's the violation I see at 85KHz...
# status: 187062600 generate 'start', write cmd 20 (slave
address+write). Check invalid address
# ** Error: i2c_slave_model.v(342): $setup( negedge sda &&& scl:1881 us,
negedge scl:1885200 ns, 4700 ns );
# Time: 1885200 ns Iteration: 1 Instance: /tst_bench_top/i2c_slave
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