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Message
From: Guy Hutchison<ghutchis@g...>
Date: Fri Jan 21 18:57:46 CET 2005
Subject: [oc] Memory Model in Verilog
It's actually not that straightforwards if you want it to be real HDL
code. It's three operations (read from memory, increment, write back
to memory), and you have to make it look like one operation to the
outside world.
If you have certain guarentees (like you'll only get one request every
3 or more clock cycles), it's easy; if you need to read more often
that than, you have to deal with write-after-read hazards.
- Guy
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