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Message
From: karthikmc at gmail.com<karthikmc@g...>
Date: Thu Jan 20 21:11:29 CET 2005
Subject: [oc] Memory Model in Verilog
Hello Everyone,
this is my first message to the forum. I am a student working on a
digital design which requires a 256 * 8 bit memory. The functionality I
require is as follows.
1> the location addressed by the 8 bit address should be checked for
its contents.
2> every time a particular location is addressed, its contents should be
incremented by a specific step (say one).
I know it is a pretty straightforward code in verilog, but I am finding the
(almost)simultaneous read-write hard to code, since I am quite new to
the nuances of verilog.
I would request the members of the forum to please suggest methods to
code the above memory model.
Regards,
Karthik
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