|
Message
From: Víctor López<victor.lopez@o...>
Date: Wed Jan 12 14:30:19 CET 2005
Subject: [oc] I2V slave implemantation in VHDL ---> Licensing issue
Wow, "I'll just do a simple translation of the Verilog version on Opencores." I wouldn't write in the same email that phrase and follow it with a price tag of "3500$", simple things don't cost that much, you must be kidding. Anyways now we run on a license issue, the copyright notice I found in one of the source files is as follows:
//// Copyright (C) 2001 Richard Herveille //// //// richard@a... //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// (followed by the typical "no warranty" disclaimer in upper case)
Is the translation of this copyrighted material a derivative work? I'd say yes May the translation be done? nothing forbids it May the translation be sold? nothing forbids it, only common sense if the price is 3500$ the only restriction is to maintain the copyright notice and disclaimer, am I missing something? I don't see why do you say, Mr. Herveille, that Mr. Brorson can't do it. Can you explain that point? If he can't modify it and sell it... is it an open-core? This is why we should have a clear license, so this issues wouldn't arise. Regards,
Víctor López
>>-----Original Message----- >>From: cores-bounces@o... >>[mailto:cores-bounces@o...] On Behalf Of Stuart Brorson >>Sent: Tuesday, January 11, 2005 1:42 PM >>To: cores@o... >>Subject: Re: [oc] I2V slave implemantation in VHDL >> >>Hi Ranga -- >> >>I'd be happy to supply you with an I2C slave core. I'll just >>do a simple translation of the Verilog version on Opencores. >> >>First you need to arrange a bank check, drawn on an American >>bank, for US$3500. Send me the check, and when it clears >>I'll be happy to e-mail you the source files. I'll send you >>the address of-line, if you agree to these terms. >> >>By the way, I'll be happy to throw in the testbench for free! >> >>Your pal, >> >>Stuart >> >> >> >> >>>Hi All, >>> >>>any body can share the I2C slave model for implementing in VHDL? It >>>will be more helpful if u can giveme the testbech also.. >>> >>>thanks in advance.. >>> >>>S.RANGA REDDY >>>_______________________________________________ >>>http://www.opencores.org/mailman/listinfo/cores >>> >>> >>>
|
 |