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Message
From: John Sheahan<jrsheahan@o...>
Date: Thu Dec 30 23:28:03 CET 2004
Subject: [oc] RS232 WB Controller freezes on Xilinx FPGA
tc27@s... wrote:
> Hi, I'm running the RS232 WB controller core as a master (without any
> other masters) and its connected to the GPIO WB core. It functions
> fine, but I've been noticing that it freezes. I divide a 100 Mhz
> clock by 2, 4, or 16, and wether its running at 50Mhz or 6.25Mhz, the
> rs232 module stops responding to serial characters usually in under a
> minute.
>
> After playing around with it all for a day or two, I've noticed that
> when I clock all the components using a global CLK line on the Xilinx
> FPGA, that is when it freezes. When I allow it to use a local clock
> (with multiple flip flop sources) then its all stable for hours
> (ofcourse the skew is really bad ~ 3ns), but it functions fine.
>
> I was wondering if anyone else could tell me how I should next debug
> this? I've only taken a single course on FPGAs and VHDL, it was
> rather introductory. I think it might be something with hold times?
> or setup times? I'm not sure.
I'd guess you have a state machine that depends on an input registered
in a different clock domain to the one the state machine uses.
part of the state machine sees an edge of that signal, and part does
not. Being xilinx, a one-hot state machine has degenerated to the
no-hot state. The fire went out.
solution - always register all signals used to control state machines
with the same clock the state mahine uses to transition.
john
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