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Message
From: Guy Hutchison<ghutchis@g...>
Date: Tue Dec 21 19:28:53 CET 2004
Subject: [oc] Dealing with large vectors in Verilog
The answer depends somewhat on whether you want the reuslt to be
synthesizable. The easiest way is to simply access the elements by
bit-slice:
reg [351:0] tmp;
tmp = MEMA[p];
result = tmp[(j+1)*16-1:j*16] + tmp[(k+1)*16-1:k*16];
However, some simulators and most synthesis tools will not accept this
syntax. Shift notation is less intuitive but works better with the
language:
reg [15:0] tmpa, tmpb;
mpa = MEMA[p] >> (j*16);
tmpb = MEMA[p] >> (k*16);
result = tmpa + tmpb;
For synthesis, this might generate acceptable results, but for
hardware it would be better to explicitly declare the two 22:1 muxes
and add the results.
- Guy
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