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Message
From: Joe Bruce<psujobu@h...>
Date: Wed Dec 1 13:56:05 CET 2004
Subject: [oc] Bug / Bug Fix: uart16550 timeout interrupt
Hi, Dalton,Unfortunately I cannot provide the entire SOPC Builder component. However,
I have attached a gzip'ed context diff (suitable for use with 'patch', which
is included with the Altera Nios II SDK) that contains the changes to the
Verilog code. From that point, you simply import the Verilog into SOPC
Builder via the "Interface to User Logic" component - see AN333 for detailed
instructions. That portion of the work only takes about 15-30 minutes, and
the whole port took 5 hours.
Note that in my own version, I renamed "wb_*" to "avalon_*". I changed the
names back in order to generate a more concise diff. Also note that a
couple changes were made based upon warnings during synthesis (e.g., unused
wire 'rbit_in'). I didn't bother porting the 32-bit interface -- I only
made the 8-bit interface (8 bits per every 32 bits of address space) work.
Finally, note that I do not register the Avalon signals, as the majority are
already registered. Perhaps this is a poor design choice on my part - I
have about four weeks of Verilog experience on top of 10+ years as an
embedded software engineer. In other words, this comes with even less of a
"no warranty" than the uart16550 core. ;-)
FYI, in my Cyclone-based design, each instance of the UART consumes
approximately 1K LEs and zero memory bits.
Regards,
Joe
----Original Message Follows----
From: avalon.diff.bin
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