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I have ported the 'uart16550' core for use with the Altera Nios II

Hi, Joe.
Looks like you're right. I did the change and commit it to the opencores. 
Thanks for the report.

Best regards,
    Igor

On Sun, 21 Nov 2004 11:24:07 -0500, Joe Bruce <psujobu@h...> wrote:
> I have ported the 'uart16550' core for use with the Altera Nios II
> processor.  This involved replacing the WISHBONE bus interface with an
> Altera Avalon bus interface - essentially removing the uart_wb.v file,
> changing some signal names, and using the 8-bit data bus.
> 
> I am using the core with some existing code that was driving a 16C752, with
> some minor modifications to eliminate 16750-specific features such as
> Auto-RTS and programmable Tx / Rx interrupt trigger levels.  The issue I saw
> was an immediate Timeout interrupt, but with no characters present in the Rx
> FIFO.  Given the ISR logic I use, the ISR never returns - I don't read from
> the RHR unless there is something in the FIFO (as reported by the LSR).
> 
> Perhaps other code works "properly", but I believe only by coincidence.  I
> believe a bug fix to the ti_int signal is required for 16x50-compatible
> behavior.  I changed line 753 of uart_regs.v from:
> 
> assign ti_int   = ier[`UART_IE_RDA] && (counter_t == 10'b0);
> 
> to:
> 
> assign ti_int   = ier[`UART_IE_RDA] && (|rf_count) && (counter_t == 10'b0);
> 
> This makes sense, since there shouldn't be a timeout interrupt unless the Rx
> FIFO has at least one character in it.  Could one of the IP core maintainers
> comment on the correctness of this bug fix?  I am now completely happy with
> the uart16550 core, but I wanted to share this change with the community...
> 
> Thank you,
> Joe Bruce
> 
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