OPENCORES.ORG

I don't have experience of Xilinx easypath, but I do have one or two

where I think XILINX saves money is that it needs to only do a functional
test of the design with test vectors provided by the designer... so that
board testing time which runs out to quite  a lot if the complete fpga chip
is to be tested. i think its a rather smart way to sell defective dies...
one question..does anyone know of any tapeouts on easypath...just curious..
    thanks and regards
        Unmesh

----- Original Message -----
From: <anon@a...>
To: <cores@o...>
Sent: Thursday, October 28, 2004 9:20 PM
Subject: Re: [oc] XILINX easypath solutions

> I don't have experience of Xilinx easypath, but I do have one or two
> things to offer in response to your questions:
>
> Xilinx easypath is a service where Xilinx reduces its post-manufacture
> test set to only cover the device's suitability for a particular
> bitstream. So, when a product is ready to go to market, the customer
> provides Xilinx with their bitstream and it is used to confidently
> pass devices that would otherwise be failed.
>
> A trivial example: A design uses only 80% of the embedded multiplier
> units in a Virtex II part. As long as the multipliers made use of are
> operational who cares if the other multipliers are working? Note that
> if the bitstream changes (e.g. bug correction) there is no guarantee
> that it will work on easypath devices passed for the initial bitstream.
>
> It is interesting to note that over 90% of the programmability in the
> routing fabric is effectively "don't care" for any single design.
> Usually the device must be tested to ensure that all features are
> working before it can be shipped to the customer.
>
> I would bet Xilinx only offers Easypath on the larger devices. This is
> because manufacturing defects increase with the silicon area of the
> device. The smaller devices will have close to 100% yield and there is
> nothing to be gained from reducing the test set through easypath.
>
> ----- Original Message -----
> From: unmesh<unmesh@s...>
> To:
> Date: Thu Oct 28 06:52:46 CEST 2004
> Subject: [oc] XILINX easypath solutions
>
> > Hi All
> >  if wonder if anyone has any info on XILINX easypath solutions?
> > have there been any design tape outs on easypath FPGAs.
> >  Thanks and regards
> >  Unmesh
> > -------------- next part --------------
> > An HTML attachment was scrubbed...
> > URL: attachment.htm
> >
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores

Scanned by the SecureSynergy VirusScreen Service. 
For more information log on to : http://www.securesynergyonline.com or http://www.securesynergy.com