LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: John Sheahan<jrsheahan@o...>
    Date: Fri Sep 17 12:09:54 CEST 2004
    Subject: [oc] setup time,hold time and clock skew
    Top
    wjx197733@e... wrote:

    > Though consult so many data,I can not understand the conception
    >about setup time,hold time and clock skew.Do the setup time have
    >relation with hold time?if have,what is the relation?Do setup time and
    >hold time have relation with the clock skew?if have,what is the relation?
    >what relation do the three conception have with the data out?
    >_______________________________________________
    >http://www.opencores.org/mailman/listinfo/cores
    >
    >
    Setup time is the time before the clock edge that data must be stable.
    The latest time it may hange if you want to predict the answer.
    Hold time is the time after the clock edge that data must be maintained
    stable.
    meaning you keep the data constant from the setup time limit until
    the hold time limit.

    In reality - the flipflop has a limited window where it actually samples
    the data. It is
    between the setup limit and the hold limit. That window will be bigger,
    as there are
    other uncertainties.

    If you transition in the window, you may get a metastable. Where the
    flipflop makes a
    long time making up its mind which way to flop.

    Clock skew is a measure of when the clock actually gets to different
    flipflops in the same design. Obviosly clock skew may result in hold
    time violations
    if its bad enough.

    the flipflop will have a clock-> q spec. as long as you don't hit a
    metastable
    (by violating setup and hold - its not always clear which one you got wrong)
    clock->q will not be affected by the prior.

    john



    ReferenceAuthor
    [oc] setup time,hold time and clock skewWjx197733

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.