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Message
From: a_roald at hotmail.com<a_roald@h...>
Date: Thu Sep 16 02:46:05 CEST 2004
Subject: [oc] Question on MIIM of Ethernet MAC Controller
While NoPre is 1, RStat is 1 and BitCounter is 0, SerialEn and ShiftBit is
enable.
When ShiftBit is assigned to Mdo, it is after two Mdc cycles. At that
time, BitCounter is 34.
While BitCounter is 48, MdoEn is disabled. But MdoEn only has 14 Mdc
cycle, it can't output the last two bit {1, 0}. So I was confused about
this.
Thanks
Haojian Zhuang
----- Original Message -----
From: Igor Mohor<igorm@o...>
To:
Date: Wed Sep 15 11:28:21 CEST 2004
Subject: [oc] Question on MIIM of Ethernet MAC Controller
> Hi, Haojian.
>
> Why don't you take something simpler for a start?
> MdoEn is delayed 2 cycles because it works with the combination
> with Mdo
> (that can be changed twice).
> Look at the Mdo and you should understand.
> Regards,
> Igor
> > I'm a newbie. So I select Ethernet MAC Controller project as
> my first
> > studying project.
> >
> > While I am reading the MIIM of the controller, I am confused
> by
> > eth_outputcontrol.v.
> >
> > In this file, MdoEn_2d, MdoEn_d, MdoEn are used. While MdoEn
> is
> > replaced by MdoEn_2d, it will cost 3 MDC cycle. ShiftBit will
> be sent on
> > Mdc rising edge. Is MdoEn delayed by 2 MDC cycle? I'm
> confused. Could
> > you help me?
> >
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