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Message
From: John Sheahan<jrsheahan@o...>
Date: Thu Sep 9 11:54:17 CEST 2004
Subject: [oc] hierarchical RTL code to html/block diagram
xemacs and vhdl/verilog-mode and speedbar is another alternative.Ricky Nite wrote: > Hello, > > Is there a tool to translate existing hierarchical RTL code (multiple > levels of module instantiations) to browsable html or block diagram? > > Im looking at HDLMaker from Polybus, but it seems to require > redefining the hierarchy/ module connections using tool-specific > *.top files, so I still have to translate the top-level RTL files to > *.top files before I can use the html/block-diagram generation feature... > > help, > > ricky n. > > ------------------------------------------------------------------------ > Do you Yahoo!? > Win 1 of 4,000 free domain names from Yahoo! Enter now > <http://us.rd.yahoo.com/evt=26640/*http://promotions.yahoo.com/goldrush>. > >------------------------------------------------------------------------ > >_______________________________________________ >http://www.opencores.org/mailman/listinfo/cores >
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