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Message
From: nico at seul.org<nico@s...>
Date: Tue Aug 31 13:24:36 CEST 2004
Subject: [oc] Parallel Array Processor Project
> Nico wrote:
>> I fund this :
>> http://www.di.ens.fr/~jv/HomePage/pdf/fpga99.pdf
>
> This was interesting! Thanks for all others, too, for the links and other
> things.
>
> The model in FPGA99-document has a lots of design issues I'm
> interested in - the most interesting for me is the use of "narrow" (4-bit)
> ALU and chained arithmetics, which is one of the corner stones in my
> design (I decided to initially start from 8-bit ALUs, just to make the
> things easier at first).
You you want power, the "good width" is better. With an 8 bits alu, you
will need 4 times it for 16 bits op. Almost twice the ressource of a true
16 bits alu.
So if target DSP market, datapath of 16 or 18 bits will deliver "more
usefull" power.
>
> Yes and I agree with the writers and many other people, that using
> programmable data flow engines probably come first as a coprocessors
> between regular CPU and DMA/memory (the CPU configures the DFE and
> puts data flow through it), altought I'm not personally interested about
> designing such thing :-)
Such pure arythmetic array quite bad for control. But mix of cpu +
datapath could do what you want at the beginning : create some VM for java
or perl.
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