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Message
From: markus at reaaliaika.net<markus@r...>
Date: Tue Aug 31 10:03:12 CEST 2004
Subject: [oc] Parallel Array Processor Project
Nico wrote:
> I fund this :
> http://www.di.ens.fr/~jv/HomePage/pdf/fpga99.pdf
This was interesting! Thanks for all others, too, for the links and other
things.
The model in FPGA99-document has a lots of design issues I'm
interested in - the most interesting for me is the use of "narrow" (4-bit)
ALU and chained arithmetics, which is one of the corner stones in my
design (I decided to initially start from 8-bit ALUs, just to make the
things easier at first).
Yes and I agree with the writers and many other people, that using
programmable data flow engines probably come first as a coprocessors
between regular CPU and DMA/memory (the CPU configures the DFE and
puts data flow through it), altought I'm not personally interested about
designing such thing :-)
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