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Message
From: Gunnar Dahlgren<gunnar.dahlgren@a...>
Date: Mon Aug 23 16:25:46 CEST 2004
Subject: [oc] Parallel Array Processor Project
At 15:00 2004-08-23 +0200, markus@r... wrote:
>
>> [...] might be that the FPGA architectures have even
>> simpler processing cells than the ones you have in mind?
>
>That's true. What are the differences of the FPGA cell and the PM cell?
An FPGA cell basically consists of a look-up-table (LUT) with four
binary inputs and one binary output. At the output there is a one-bit
register (flip-flop). The LUT can be programmed by a 16-bit word
(= "the program"), whose bits are the value of the output for the
2^4 possible combinations of the inputs.
In reality, the basic cell of the FPGA is a little bigger, containing
a few LUTs and flip-flops, and some multiplexers to allow the LUTs to
be combined in different ways.
The "program" of each LUT is normally loaded during boot-up configuration
and then stays the same. But also see below.
I guess the PM cells are at least a few bits wider, but what other
differences are there?
>...
>I could quickly think these differences:
>
>* The PM design should allow you to write programs for writing programs
>(e.g. compilers, text editors and so on). I'm not sure, if you could write
>a VHDL/FPGA compiler to FPGA?
You can. If not in other ways, you can implement a traditional CPU in
the FPGA to do it... :-)
I believe (without knowing) that this would also be the most efficient
way of implementing a compiler in an FPGA. But I guess it should be
theoretically possible to actually implement a compiler as general
hardware (FSMs, datapaths...), which reads source code from a connected
memory, and produces machine code in another part of the memory.
I wouldn't like to design that hardware though. Hardware design (at
RTL level) can be said to be at an abstraction level below assembly
programming, and I guess most programmers would be very unhappy even
to have to write a compiler in assembly language.
This shall, however, not be confused with the general abstraction
level of VHDL (or Verilog). Only subsets of the languages are
synthesizable (ie possible to use to describe RTL hardware). You can
use those languages to write code at a somewhat higher abstraction
level as well, but then it can only be executed in a simulator (ie on
an ordinary CPU). It can not be executed in an FPGA fabric, due to
that we don't have tools for synthesis/compilation of the complete
languages. Such tools have long been attempted, Celoxica's tool is
one attempt (although it uses a C-ish language instead of VHDL/Verilog).
>* Furthermore, PM design should allow a program to "load" another
>program inside the array. If I recall correctly, there has been some
>attempts for creating "self-reconfigurable" FPGAs, too? But because of
>the application area of the FPGA, I think that those oddities are not
>very popular...?
No I'm not sure if the feature is used a lot, but it is possible in
e.g. Xilinx Virtex FPGAs. I also think Celoxica developed a demonstrator
a few years ago that used this feature. (some kind of PDA-like thing
with the possibility to run a few different "applications", the selected
one were then loaded from memory into (parts of) the FPGA. The
demonstrator didn't have a normal stand-alone CPU chip, but surely had
one or several soft CPUs in the FPGA.
(no, I'm not a Celoxica sales rep, I have no connection whatsoever with
them... ;-)
>
>* The PM chip should be able to execute larger programs that can fit
>inside of the chip, by using a virtual memory. Normally, you don't have
>this kind of possibilities in the FPGA, am I right?
Not normally used, but not at all impossible I would say.
Regards
Gunnar
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