LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Joachim Strömbergson<Joachim.Strombergson@I...>
    Date: Tue Aug 17 11:01:48 CEST 2004
    Subject: [oc] Parallel Array Processor Project
    Top
    Aloha!

    markus@r... wrote:
    >>You mean you have a pcode generator? ;-)
    >
    > Well, I didn't quite follow this... Most parsers/compilers (including most
    > of my compiler constructions and the current PM HLL compiler) convert
    > the mixed prefix/infix notation (function calls, infix operators) to a
    > postfix, stack-based code. Then, for conventional processors, a register
    > allocation is done and the compiled code is emitted.

    Which is called p-code after the UCSD p-code machine. Used heavily in the
    early compiler research and was related to Pascal. See:

    http://en.wikipedia.org/wiki/P-Code_machine
    http://en.wikipedia.org/wiki/Pascal_programming_language
    http://www.fact-index.com/p/p_/p_code_machine.html

    Normally though you use the p-code to build trace trees and then optimize on
    them, perform register allocation, instruction selection, new optimization
    pass etc etc before generating code for the non-stack-processor. Unless the
    target is a stack machine like Python or Java byte code etc.

    > I know - what a mess :-( But, the assembler programming is much
    > harder for larger applications than programming tweaked C code... :-/

    That's why people buy a faster DSP instead and take the overhead [1], esp for
    first, second product releases. Converting code to assembler and other
    optimizations are saved for nmanufacturing cost reduction after the product
    have successfully been released onto the market.


    [1] And if you look at TI 6000, AD TigerSHARC etc, most programmers have a
    hard time beating the performance reached by the compilers by hand writing
    asssembler. Few people are able to easily grok multiple executin, instruction
    pairing. This is especially true if the architecture is non-orthogonal which
    introduces lots of rules for instruction scheduling, register allocation,
    instruction pairing, pipeline allocation etc etc.
    --
    Med vänlig hälsning, Yours

    Joachim Strömbergson - Alltid i harmonisk svängning.
    VP, Research & Development
    ----------------------------------------------------------------------
    InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden
    Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02
    E-mail: joachim.strombergson@i... Home: www.informasic.com
    ----------------------------------------------------------------------



    ReferenceAuthor
    [oc] Parallel Array Processor ProjectMarkus

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.