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Message
From: Joachim Strömbergson<Joachim.Strombergson@I...>
Date: Tue Aug 17 10:51:35 CEST 2004
Subject: [oc] Parallel Array Processor Project
Aloha!markus@r... wrote:
> Thanks! I already took a quick look. The F21 could be striped down
> more, when using in the array. There's no need for subroutines, jumps
> and conditionals are enough. Thus, there's no need for PC stack, either.
> The data stack could be decreased, too.
Remember to strip you compiler if you kick out subroutines. They really don't
cost that much in stack machines.
> What increases the complexity, is the neighborhood synchronization - it
> could be HW or SW based, which ever seems to be better. I would
> prefer software-based, because:
>
> * You would implement only that synchronization mode, which you're
> using in the cell (with HW implementation, you'd need to implement all
> modes to all cells)
>
> * It could give you possibility to use very complex synchronizations.
Did you see my comments on the PORT semantics for stack machines?
What you probably want are three primitives:
(1) An IN port directive. Read from a shared memory via the port system. The
address could be implicitlt taken as the value on TOP on the data stack.
(2) An OUT port directive. Write to a shared memory via the port system. The
address and value could be implicitly taken as TOP and TOP+1 on the data stack.
(3) An atomic test and set ("TST" perhaps), a semaphore. Either a binary or
multi value semaphore where the set value is TOP.
The HW implementation for (1) and (2) would need to consider write scheduling
and/or memory segmentation (dedicated write areas per PE), the latter would
directly affect the programming model.
(3) can be quite simply implemented by restricting the area where TST can be
performed. I.e. they are located in a separate area from the shared memory.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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