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    Navigation: All forums > Cores > Message List > Message Post

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    From: nico at seul.org<nico@s...>
    Date: Mon Aug 16 14:11:56 CEST 2004
    Subject: [oc] Parallel Array Processor Project
    Top
    >> markus@r... wrote:
    >> > My area of intrest is MIMD and I'm very aware, that the
    >> > architecture I'm currently planning won't beat SIMD-processors
    >> > or systolic arrays in their strong area. That's not a target for
    >> > the project; the target is to design architecture and tools
    >> > for general purpose parallel processor.
    >> >
    > [...]
    >> The problems I see with building massive MIMDs on anything (cabinet
    >> or chip) is program model and communication.
    >
    > You're absolutely right here - the programming model is terrible. In the
    > early 90's, when I was last time working on this project, I was
    > convinced, that the difficultiness of programming makes the model
    > unusable. And altought I now have over 10 years more experience of
    > programming, including parallel systems, with a strong motivation for
    > solving the thing, it's still hard and desperous mission.
    >
    > But, most of you are probably familiar with VHDL - that's one of the
    > existing parallel languages and you probably know, that it's not
    > impossible to make something usable with it, and it's even possible to
    > make the code somewhat understandable, too.
    >

    For a large scale small cpu array, VHDL could do a great job i beleive.


    [...]

    >> Fortunately, with nano-technology if some wild ideas are to go by,
    >> we should be able to get basically as much computing power as
    >> we are going to need EVER:
    >> http://www.aeiveos.com/~bradbury/MatrioshkaBrains/index.html
    >
    > Yes, here's the goal! ;-)
    >
    > But seriously, one can imagine computer systems like that, but how are
    > they programmed? In which language? How are the processing cells
    > constructed (instruction set, memories, external connections, etc)?
    > What kind of memory bus those computers have? What kind of
    > peripherals?

    I think the best model is a PC cluster. Every node contain memory and is
    linked to the closest other cell. Then the routing algorithm could be
    fractal like.


    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores
    >


    ReferenceAuthor
    [oc] Parallel Array Processor ProjectMarkus

     
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