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    From: Unmesh<unmesh@s...>
    Date: Fri Jul 30 08:19:58 CEST 2004
    Subject: [oc] VERA Query
    Top

    Hi
    I have a query regarding VERA. Is it possible to connect a variable defined in a class to be connected to a port defined in the interface (.if.vrh) file.

    example:

    i have a class in which a variable rst has been declared as a bit. the reset is being pulled high @(posedge CLOCK). i also have a hdl from which i have a generated a if.vrh file which has a port called reset. I want to connect the variable rst to the port reset. this is especially critical to me because i want to generate all the stimulus inside a class and then plug in this class and test the hdl. final objective is reusability.


    thanks and regards
    Unmesh Khadilkar
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