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Message
From: markus at reaaliaika.net<markus@r...>
Date: Thu Jul 15 09:55:48 CEST 2004
Subject: [oc] Parallel Array Processor Project
[multiport memories]
> With a cellular automata design you can get away with two port
> memory because you only have
> the processor and it's neighbour accessing shared memory.
Yes, true. I just try even simpler. Altought last night when I was waiting
for sleep I realized, that there could be some use for cell operations,
which could change the state of the neighbor. But I must refine my
instruction set to see it...
[stand-alones]
> You need some mass storage, and usually this is localise to one of
> the CPUs. To keep the design symetrical I was going to use the 6809
> to load and save code by using the dual port facility of
> the Xilinx Block RAM. There is no reason why the 6809 can't be on
> the same chip. It was only a size constraint of the FPGA.
Of course. Normally, when I'm scetching a virtual processor core, I left
the code download issues (just like MMU's and such) out of the design
at the first phase. But the concept I'm scetching now is different
enough from my other designs, that I think it's important for me to keep
in mind (and scetch), how to implement programs with the array to
program the array.
If I am ever going to make a prototype out of the design, I probably
leave the programming issues last ones to try out. Before that, the
array is programmed by an external controller (e.g. PC).
> > a little bit sceptic, if the 2-layer "cube" would
> > give anything new you
> > haven't seen already. I place my hopes to future IC
> > manufacturing
> > technologies... :-)
> >
> I attended an FPGA conference in the UK back in 1997. There was a
> paper on 3D semiconductor design ...
I have always believed, that chip manufacturers "waste" lots of money
to develop processes for stacked transistor layers. That would benefit
regular processor (and memory) implementations too.
[cellular automatas]
> > Yes, this was the "magic word" I'd forgot! Thanks,
> > I'll go to the web to
> > search more information.
> >
> I was interested in using Cellular Automata for image processing at
> one stage, but the FPGA chips were too small at the time to do
> any thing serious ...
[...]
In your description, you covered some of the problems I have with my
design. Altought the whole project started to go around the problem of
external memory bandwidth, AFAIK it still have a significant effect to the
overall performance of the algorithms.
And yes, it's quite a problem and waste of cells (and more importantly,
waste of space), that only the few cells have something useful to do,
while most of the cells just stay idling or moving data.
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