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Message
From: arniml at opencores.org<arniml@o...>
Date: Mon Jul 12 23:11:59 CEST 2004
Subject: [oc] C16 processor
Hi Kevin,
> The problem also occurs with just the post-translation simulation
> (not just post-Palce and route).
> The problem is not dependent on clock rate (it fails even while
> single stepping at 1Hz in the FPGA).
So we're not looking at a performance (setup) problem?!
> so it would seem that the most likely scenario is that the new
> Xilinx tools interpret the code differently from the simulation.
Probably yes. Can you make sure that
a) all sensitivity lists are complete?
b) signals carrying clocks are not assigned further to signals ("clock
renaming")?
c) the functionality of the netlist and the RTL VHDL are equivalent?
a) and b) are likely to cause different behaviour of the RTL and
gatelevel (synthesized/translated) designs. c) would discover compiler
errors but requires a separate tool for formal verification.
Cheers
Arnim
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