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Message
From: kevinjwhite at comcast.net<kevinjwhite@c...>
Date: Mon Jul 12 02:55:45 CEST 2004
Subject: [oc] C16 processor
Arnim,Yes - you're right. It fails with the post-place and route simulation. I
hadn't done that because somebody else said it was difficult to do with
Modelsim...
I wonder what causes the behavioural simulation to work but the post-
place one to fail?
thanks
kevin
----- Original Message -----
From: arniml@o...<arniml@o...>
To:
Date: Sun Jul 11 22:28:11 CEST 2004
Subject: [oc] C16 processor
> Hi Kevin!
>
> > I can see that the instructions are in memory OK. Its
> > as if the Xilinx tools are not synthesizing the VHDL
> correctly.
> > Any hints will be welcome.
> Have you considered to simulate the post place & route design?
> ISE can
> write a VHDL netlist of the design after P&R and simulating it
> should
> show the same problem. I never tried this with Modelsim, maybe you
> have to compile some Xilinx-specific libraries.
> Good luck!
> Arnim
>
>
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