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Message
From: grozzy at cox.net<grozzy@c...>
Date: Sun Jun 20 21:43:15 CEST 2004
Subject: [oc] Synthesis assistance required
Memories are always tricky as has been pointed out. I've been designing
chips and FPGAs for years and they always offer a challenge. In general
before you can really do the design you need to understand the
underlying memories available to you in your target technology. This is
key. Although every company i work at tries to create generic memory
types, FIFO, 1 port, 2 port, sync/async read/write ... some
combinations don't work with a vendor or FPGA library due to the
underlying memories.
Why not just use flops? Way too big and a routing nightmare. This is
even a greater problem in FPGAs.
So is your design actually implementable in an FPGA/ASIC? Probably not
since you can't truely parameterize a memory, since the underlying
cell/macro size is fixed. You can paramterize the logic around the macro,
but not the memory macro itself.
The general flow is
RTL -> (synthesizer) -> netlist -> (fitter/P&R) -> implemented design.
For people learning now, it is much better since there are many free
tools and the FPGAs offer a cheap implementation target to practice
with.
I would
1) get a synthesizer somehow.
2) i would target an FPGA, get the free software, read the docs, and
build your core to use their underlying memories.
3) next synthesize using their directions, fit to the device, read the
timing reports, etc etc till you get a design that really works. aka meets
timing, uses a reasonable amount of logic, etc
It sounds like you have done a good job on the front end. Now work on
the back-end. This is critical. A design that doesn't meet timing is not a
design. A design that uses a large flop array instead of a memory macro
is not a design. They are science experiments. Actually i wish i only had
to due science experiments :)
--Mike
----- Original Message -----
From: Unmesh<unmesh@s...>
To:
Date: Wed Jun 16 11:20:05 CEST 2004
Subject: [oc] Synthesis assistance required
> I am developing a fully synthesizable 32 bit FIFO with programmable
> depth in verilog. AMBA APB compliance features have also been added
> to the design. I have completed the RTL and the functional
> verification. I need assistance w.r.t synthesizing the core ( both
> FPGA and ASIC will do ). Assistance will be greatly appreciated.
> Thanks and regards
> Unmesh
> unmesh@s...
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