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Message
From: Unmesh<unmesh@s...>
Date: Wed Jun 16 11:20:05 CEST 2004
Subject: [oc] Synthesis assistance required
I am developing a fully synthesizable 32 bit FIFO with programmable depth in verilog. AMBA APB compliance features have also been added to the design. I have completed the RTL and the functional verification. I need assistance w.r.t synthesizing the core ( both FPGA and ASIC will do ). Assistance will be greatly appreciated.
Thanks and regards
Unmesh
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