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Message
From: Michael M Delaney
Date: Sat Jun 5 19:19:28 CEST 2004
Subject: [oc] Newbie : Synthesizable verilog to hspice
Most universities seem to be worried about people using university tools
for something leading to making money (such as designing a new product, or
"borrowing" a copy for the company they work for. You might want to ask
first, but I think they will not have a problem with you working on some
open source designs with their tools. I'd say give it a shot, unless one
of the restrictions on the tools was access to a computer running them.
Mike
On Sat, 5 Jun 2004 sreekumarvk@r... wrote:
> Hi,
>
> Thanks for the detailed reply. I am a student and my university has
> some of the tools which you had mentioned, namely hspice and some
> synopsys tools for synthesizing vhdl/verilog code. I am looking to do
> some timing analysis in hspice for some of the cores present in the
> website. Since typing out big cores in hspice is not possible, I was
> thinking of converting VHDL/Verilog models into Hspice. I am familiar with
> hspice and to some extent these synopsys tools. But havent tried
> combining it till now. I dint know if this was possible, so was wondering
> if there is a way in which it can be done. Since the tools were owned by
> the university and there are some restrictions in using it, I was
> wondering if there are any opensource tools available using which I can
> get the job done. From your mail, I guess I will have to use the
> commercial tools.
>
> Thanks for the details. I will look around more and try out stuff.
>
> Thanks
>
> Sreekumar
>
> ----- Original Message -----
> From: John Sheahan<jrsheahan@o...>
> To:
> Date: Sat Jun 5 07:29:34 CEST 2004
> Subject: [oc] Newbie : Synthesizable verilog to hspice
>
> > In general, a RTL core describes behaviour, not a transistor
> > specific
> > implementation.
> > Hspice is a commercial spice simulator, with a few extensions to
> > basic
> > spice.
> > spice is typically used to give accurate simulation (and timing) of
> > a
> > specific path
> > in the logic. Life is too short to simulate much functionality with
> > spice.
> > Use verilog or vhdl if thats what you want.
> > The steps you would take to get a spice netlist - if you want the
> > accuracy spice is usually used for -
> > essentially are:
> > choose a target silicon technology. Get the cell libraries from the
> > vendor.
> > You want the cell spice libraries, layout libraries, synthesis
> > libraries.
> > write timing constraints for the rtl module
> > synthesize the module, using the timing constraints and the
> > synthesis
> > libraries
> > (design compiler or buildgates are the usual non-free suspects
> > here)
> > you would usually get a verilog gate level netlist out of this
> > step.
> > place and route the logic. interconnect delay matters a lot these
> > days.
> > If you want spice accuracy -
> > you need real wires. You will want the timing constraints to guide
> > this
> > step too.
> > use a parasitic extraction tool to spit out the spice netlist -
> > complete
> > with all the interesting
> > capacitances between wire segments.
> > there are free tools to do some of these steps to varing degrees of
> > accuracy.
> > But hspice is not free. If you have a synopsys hspice license - you
> > may
> > have the
> > DC and avanti tools to do the other steps too.
> > a lot of the above can be simplified if accuracy is not an issue.
> > But
> > then why spice?
> > john
> > sreekumarvk@r... wrote:
> > >Hi,
> > >
> > >Thanks for the information, John. I am interested in the hspice
> > version
> > >of some of the synthesizable verilog/vhdl code present in
> > opencores.org.
> > >I am pretty new to verilog/vhdl. Can you tell me how I should
> > go about
> > >doing it or point to me a link/book where they have the
> > information?
> > >Tools which I would require ( any of which are freely available
> > or
> > >opensource) and steps to follow, ( any script which can
> > automate the
> > >process). I tried googling, but couldnt get useful link :(.
> > >
> > >Thanks for the help.
> > >
> > >Sreekumar
> > >
> > >----- Original Message -----
> > >From: John Sheahan<jrsheahan@o...>
> > >To:
> > >Date: Fri Jun 4 12:30:50 CEST 2004
> > >Subject: [oc] Newbie : Synthesizable verilog to hspice
> > >
> > >
> > >
> > >>sreekumarvk@r... wrote:
> > >>
> > >>
> > >>
> > >>>Hi,
> > >>>
> > >>>I was wondering if it is possible to convert a
> > synthesizable
> > >>>
> > >>>
> > >>verilog code
> > >>
> > >>
> > >>>to transistor level hspice netlist.
> > >>>
> > >>>
> > >>>
> > >>>
> > >>>
> > >>you could always synthesize it and then swap in the hspice
> > cell
> > >>model.
> > >>
> > >>
> > >>
> > >>>Thanks
> > >>>
> > >>>Sreekumar
> > >>>_______________________________________________
> > >>>http://www.opencores.org/mailman/listinfo/cores
> > >>>
> > >>>
> > >>>
> > >>>
> > >>
> > >>
> > >_______________________________________________
> > >http://www.opencores.org/mailman/listinfo/cores > >
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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