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Message
From: John Sheahan<jrsheahan@o...>
Date: Sat Jun 5 07:29:34 CEST 2004
Subject: [oc] Newbie : Synthesizable verilog to hspice
In general, a RTL core describes behaviour, not a transistor specific
implementation.
Hspice is a commercial spice simulator, with a few extensions to basic
spice.
spice is typically used to give accurate simulation (and timing) of a
specific path
in the logic. Life is too short to simulate much functionality with spice.
Use verilog or vhdl if thats what you want.
The steps you would take to get a spice netlist - if you want the
accuracy spice is usually used for -
essentially are:
choose a target silicon technology. Get the cell libraries from the vendor.
You want the cell spice libraries, layout libraries, synthesis libraries.
write timing constraints for the rtl module
synthesize the module, using the timing constraints and the synthesis
libraries
(design compiler or buildgates are the usual non-free suspects here)
you would usually get a verilog gate level netlist out of this step.
place and route the logic. interconnect delay matters a lot these days.
If you want spice accuracy -
you need real wires. You will want the timing constraints to guide this
step too.
use a parasitic extraction tool to spit out the spice netlist - complete
with all the interesting
capacitances between wire segments.
there are free tools to do some of these steps to varing degrees of
accuracy.
But hspice is not free. If you have a synopsys hspice license - you may
have the
DC and avanti tools to do the other steps too.
a lot of the above can be simplified if accuracy is not an issue. But
then why spice?
john
sreekumarvk@r... wrote:
>Hi,
>
>Thanks for the information, John. I am interested in the hspice version
>of some of the synthesizable verilog/vhdl code present in opencores.org.
>I am pretty new to verilog/vhdl. Can you tell me how I should go about
>doing it or point to me a link/book where they have the information?
>Tools which I would require ( any of which are freely available or
>opensource) and steps to follow, ( any script which can automate the
>process). I tried googling, but couldnt get useful link :(.
>
>Thanks for the help.
>
>Sreekumar
>
>----- Original Message -----
>From: John Sheahan<jrsheahan@o...>
>To:
>Date: Fri Jun 4 12:30:50 CEST 2004
>Subject: [oc] Newbie : Synthesizable verilog to hspice
>
>
>
>>sreekumarvk@r... wrote:
>>
>>
>>
>>>Hi,
>>>
>>>I was wondering if it is possible to convert a synthesizable
>>>
>>>
>>verilog code
>>
>>
>>>to transistor level hspice netlist.
>>>
>>>
>>>
>>>
>>>
>>you could always synthesize it and then swap in the hspice cell
>>model.
>>
>>
>>
>>>Thanks
>>>
>>>Sreekumar
>>>_______________________________________________
>>>http://www.opencores.org/mailman/listinfo/cores
>>>
>>>
>>>
>>>
>>
>>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
>
>
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