OPENCORES.ORG

sreekumarvk@r... wrote:

Hi,
Thanks for the information, John. I am interested in the hspice version  
of some of the synthesizable verilog/vhdl code present in opencores.org. 
I am pretty new to verilog/vhdl. Can you tell me how I should go about 
doing it or point to me a link/book where they have the information? 
Tools which I would require ( any of which are freely available or 
opensource) and steps to follow, ( any script which can automate the 
process). I tried googling, but couldnt get useful link :(.

Thanks for the help.

Sreekumar

----- Original Message ----- 
From: John Sheahan<jrsheahan@o...> 
To: 
Date: Fri Jun  4 12:30:50 CEST 2004 
Subject: [oc] Newbie : Synthesizable verilog to hspice 

> sreekumarvk@r... wrote: 
> 
> >Hi, 
> > 
> >I was wondering if it is possible to convert a synthesizable 
> verilog code 
> >to transistor level hspice netlist. 
> > 
> > 
> > 
> you could always synthesize it and then swap in the hspice cell 
> model. 
> 
> >Thanks 
> > 
> >Sreekumar 
> >_______________________________________________ 
> >http://www.opencores.org/mailman/listinfo/cores 
> > 
> > 
> 
> 