LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: sreekumarvk at rediffmail.com<sreekumarvk@r...>
    Date: Thu Jun 3 16:29:54 CEST 2004
    Subject: [oc] Newbie : Synthesizable verilog to hspice
    Top
    Hi,

    I was wondering if it is possible to convert a synthesizable verilog code
    to transistor level hspice netlist.

    Thanks

    Sreekumar

    Follow upAuthor
    [oc] Newbie : Synthesizable verilog to hspiceJohn Sheahan

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.