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Message
From: Stuart Brorson<sdb@c...>
Date: Sun May 16 22:59:23 CEST 2004
Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools
Hello,I've been reading with great interest this ongoing discussion about
the desirability of an end-to-end design flow for chips. The reason
such tools don't exist as of now is very simple: It hasn't been worth
any knowledgable engineer's while to write them, the ASIC and FPGA
companies realize they can make money by charging for their tools, and
the universities don't find that area of work interesting or
worthwhile.
So please allow me to call your bluff: How much are you willing to
pay for a decent set of synthesis tools? I will grant that
$100K+/seat which Cadence, Synopsys, Mentor, and so on want is TFM.
On the other hand, it's clear that people are not lining up at the
door to do the job for free. To catalyze development, the possibility
of making money is required. What is an order-of-magnitude figure for
what you would be willing to pay for an end-to-end, open-source flow
with basic functionality?
Stuart
> All:
>
> A couple of things pop out of this discussion:
>
> 1) A complete -and free - backend solution is of great interest to all of
> us.
> 2) Alliance may be the closest thing we have (I haven't seen better
> alternatives proposed).
>
> How much work is it to build a useful timing tool?
> A primitive approach using verification suites and netlists with gate
> timing files and average wire load models should be pretty easy to put
> together.
> The kind of thing one gets out of DC - using netlist data only, does not
> seem (at least to me) as difficult a problem to solve
> as some that have already been solved.
>
> I guess it would be nice to have a free primetime or einstimer -- but for a
> lot of purposes, a somewhat less precise (and so more conservative)
> approach might be sufficient.
>
> Any thoughts from any of you that know more about this stuff???
>
> bj
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