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Message
From: Guy Hutchison<ghutchis@g...>
Date: Sun May 16 08:24:48 CEST 2004
Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools
On Sat, 15 May 2004 16:10:09 +0100, Shehryar Shaheen
<shehryar.shaheen@u...> wrote:
>
> Ofcourse the Alliance tools cannot be compared with Synopsys DC
> or Cadence Buildgates etc but theses tools have big price tags which
> the Allaince tools don't. Its common knowledge that free tools may
> not be wholly at par with the ones that are not free but then this
> doesn't mean that nomenclature has to be different
True, but there are also many open-source tools (not, unfortunately,
in the EDA space) which are fully the equal of their closed-source
equivalents. Your original email implied that Alliance is a
production-ready synthesis tool; in my opinion, this is not true.
> Icarus Verilog is grouped under 'Verilog Simulator' but because
> it doesn't have all the features that NC-Verilog or Verilog-XL have
> it doesn't need to called say 'half-verilog simulator' or something , now
> does it :)
No, but it was usually referred to as an "under development" Verilog
simulator in its earlier days. And mostly what I was trying to point
out is that Alliance is a synthesis tool, with caveats, and that the
caveats are sufficiently large to preclude its use for most things
outside of academic research (unless there's a static timing tool in
the set that I haven't found yet).
Lest you think I am all negative on the subject, some tools that I
think *are* production ready tools are CVer (Verilog simulator),
Dinotrace (waveform viewer) and Verilator (Verilog-to-C translator).
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