OPENCORES.ORG

> among others Logic Synthesis and place & route tools for standard

Guy & Shehryar:
I don't want to get involved in semantics and name calling  -- but would
like to understand (at least at a high level) the potential value of the
Allinace toolset.   I generally code in verilog -so have some issues there
(independent of which subset of VHDL is supported  - and how well
that subset is documented)  --  but my first impression in looking at the
toolset has been that there is no support for timing closure.
This is a serious deficiency.  Am I missing something?

bj Porcella
http://pages.sbcglobal.net/bporcella/

----- Original Message ----- 
From: "Guy Hutchison" <ghutchis@g...>
To: "Discussion list about free open source IP cores" <cores@o...>
Sent: Thursday, May 13, 2004 11:12 PM
Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools

> > among others Logic Synthesis and place & route tools for standard
>
> I've played around some with the Alliance tool set, and this statement
> is highly misleading.  While there are two tools which are called
> "logic synthesis", they would not be recognized as a synthesis tool by
> most FPGA/ASIC designers.
>
> The Alliance tools can tackle only a very small subset of VHDL, whose
> level of abstraction is roughly that of a gate level description.
> Unless something has changed since when I last looked at the tools,
> they would not be able to synthesize any of the designs found on
> OpenCores.
>
> The back-end tools are much more complete, although I don't believe
> that they are timing-aware.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores