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Message
From: Richard Herveille<richard@a...>
Date: Sat Jan 31 10:41:13 CET 2004
Subject: FW: [oc] Translation
>
> Right!
> But I want to make a process with various waits referencing to multiple
> signals/ports! At level of simulation this works! But I want to synthesize
> this code! And the program that I uses (Altera Quartus II) doesn't
> accept/support more that one wait in a process! How can I solve this?
>
Think about what you are asking and what is available in design cells.
You are asking for a circuit that triggers on multiple signals, like a
flip-flop with multiple clock inputs?
Simulation/Modulation is much more flexible in what is allowed and possible,
as the simulator just needs to execute the sequential code.
However translating this into hardware requires other techniques and a more
restrict coding style. Stick to the convention and it will work, do
something weird and you're on your own.
If you wrote a piece of code (converted or not) that is not synthesizable
and that was intended to be synthesizable, then you did a bad job. This is
not the synthesizer's fault, so don't blame it on Quartus.
Go back to the original code and rewrite it so it is synthesizable, or pay
somebody to do it for you.
Richard
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