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>From my experience, it is best to wait on just clock and reset. Only

At 14:22 30/01/2004, you wrote:
> >From my experience, it is best to wait on just clock and reset.  Only 
> trigger on one edge of the clock and one edge of the reset.  Any other 
> decisions should be done with if then statments.
>
> >From my understanding it is much easier to generate this logic.  I use 
> Verilog, and this is what my code would look like:
>
>always@(posedge i_clk or negedge i_reset_n)begin
>         if(!i_reset_n)begin
>         //reset logic here
>         end
>         else begin
>         if(sig_x==1'b1)begin
>                 //do something here
>                 end
>         end
>end
>
>If you wanted to wait for the posedge of the clock and only execute when 
>sig_x is high, this would work.  If you are doing something like a FIFO 
>where there are two clocks, you need to use seperate always blocks that 
>are clocked to different clocks.  One to write to your buffer and one to 
>read from it.  Also, if just want to cross a clock boundry, do the same 
>thing but instead of using some memory, just double buffer the signal.
>
>We might be able to help you more if you tell us specifically what type of 
>module you are trying to make.
>
>-Brian
>
>
>-----Original Message-----
>From:   cores-bounces@o... on behalf of Redant Steven
>Sent:   Fri 1/30/2004 7:10 AM
>To:     Discussion list about free open source IP cores
>Cc:
>Subject:        RE: FW: [oc] Translation
>
>The only way to make a process that waits on different signals is writing 
>a combinatorial function using all these in the sensitivity list.
>
>For synthesis you HAVE to stick to the rules. Synthesis on higher levels 
>(i.e. choosing architecture from a higher level description) is possible 
>for some specific kinds of architectures in (not free) EDA software, but 
>there is still a gap here.
>
> >> Right!
> > But I want to make a process with various waits referencing
> > to multiple
> > signals/ports! At level of simulation this works! But I want
> > to synthesize
> > this code! And the program that I uses (Altera Quartus II) doesn't
> > accept/support more that one wait in a process! How can I solve this?
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
>
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>
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I had already think in that, but the logic is ready! I have to translate 
SystemC to VHDL! 