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Message
From: Brian Korsedal<BKorsedal@b...>
Date: Fri Jan 30 17:22:41 CET 2004
Subject: FW: [oc] Translation
>From my experience, it is best to wait on just clock and reset. Only trigger on one edge of the clock and one edge of the reset. Any other decisions should be done with if then statments.
>From my understanding it is much easier to generate this logic. I use Verilog, and this is what my code would look like:
always@(posedge i_clk or negedge i_reset_n)begin
if(!i_reset_n)begin
//reset logic here
end
else begin
if(sig_x==1'b1)begin
//do something here
end
end
end
If you wanted to wait for the posedge of the clock and only execute when sig_x is high, this would work. If you are doing something like a FIFO where there are two clocks, you need to use seperate always blocks that are clocked to different clocks. One to write to your buffer and one to read from it. Also, if just want to cross a clock boundry, do the same thing but instead of using some memory, just double buffer the signal.
We might be able to help you more if you tell us specifically what type of module you are trying to make.
-Brian
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