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Message
From: Fernando Remus Nagel<frnagel@u...>
Date: Fri Jan 30 15:50:56 CET 2004
Subject: FW: [oc] Translation
At 07:21 30/01/2004, you wrote:> >
> > You do not use 'wait' to generate synchronous actions in VHDL.
> > If your translator generates this code, you'll have to
> > rewrite it so it
> > uses:
> >
> > clk'event and clk='1'
> > or
> > rising_edge(clk)
> >
> > The above is good coding practice (for synthesis)
> > Using wait isn't. Although some synthesis tools allow you to
> > use a single
> > 'wait' in a process to generate synchronous designs.
>
>
>Or use behavioral compiler with code that looks like Geert's example sent
>in a previous mail (i.e. several wait until rising_edge(clk) statements in
>one process).
>
>Steven
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
Right!
But I want to make a process with various waits referencing to multiple
signals/ports! At level of simulation this works! But I want to synthesize
this code! And the program that I uses (Altera Quartus II) doesn't
accept/support more that one wait in a process! How can I solve this?
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