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Message
From: Redant Steven<redant@i...>
Date: Fri Jan 30 10:21:28 CET 2004
Subject: FW: [oc] Translation
>
> You do not use 'wait' to generate synchronous actions in VHDL.
> If your translator generates this code, you'll have to
> rewrite it so it
> uses:
>
> clk'event and clk='1'
> or
> rising_edge(clk)
>
> The above is good coding practice (for synthesis)
> Using wait isn't. Although some synthesis tools allow you to
> use a single
> 'wait' in a process to generate synchronous designs.
Or use behavioral compiler with code that looks like Geert's example sent in a previous mail (i.e. several wait until rising_edge(clk) statements in one process).
Steven
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