OPENCORES.ORG

-----Original Message-----

You do not use 'wait' to generate synchronous actions in VHDL.
If your translator generates this code, you'll have to rewrite it so it
uses:

clk'event and clk='1'
or
rising_edge(clk)

The above is good coding practice (for synthesis)
Using wait isn't. Although some synthesis tools allow you to use a single
'wait' in a process to generate synchronous designs.

Richard

> -----Original Message-----
> From: cores-bounces@o... [mailto:cores-bounces@o...] On
> Behalf Of Fernando Remus Nagel
> Sent: Thursday, January 29, 2004 10:24 PM
> To: cores@o...
> Subject: RE: FW: [oc] Translation
> 
> >
> > > >process
> > > >begin
> > > >
> > > >...
> > > >Wait on a;
> > > >
> > > >...
> > > >
> > > >wait on b;
> > > >
> > > >...
> > > >
> > > >wait on a;
> > > >
> > > >end;
> > > >
> >
> > > Someone said me that even without a sensitivity list, the
> > > wait's must refer
> > > to a unique signal or port!
> >
> > You mean in VHDL? No that is not true from a strict VHDL lan
> guage/simulator standpoint. For Behavioral compiler it is the
> case that you should have all the waits waiting for the same k
> ind of clock-edge.
> >
> > Steven
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
> >
> Yes, at level of simulation this works. But the problem is
> that I want to synthetize this. The program that I use to
> this don't accept/support more than one wait in a process!
> How can I solve this problem?
> 
> 
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