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Message
From: Fernando Remus Nagel<frnagel@u...>
Date: Thu Jan 29 22:23:42 CET 2004
Subject: FW: [oc] Translation
>
> > >process
> > >begin
> > >
> > >...
> > >Wait on a;
> > >
> > >...
> > >
> > >wait on b;
> > >
> > >...
> > >
> > >wait on a;
> > >
> > >end;
> > >
>
> > Someone said me that even without a sensitivity list, the
> > wait's must refer
> > to a unique signal or port!
>
> You mean in VHDL? No that is not true from a strict VHDL lan
guage/simulator standpoint. For Behavioral compiler it is the
case that you should have all the waits waiting for the same k
ind of clock-edge.
>
> Steven
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
Yes, at level of simulation this works. But the problem is
that I want to synthetize this. The program that I use to
this don't accept/support more than one wait in a process!
How can I solve this problem?
---
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