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Message
From: Redant Steven<redant@i...>
Date: Thu Jan 29 17:36:55 CET 2004
Subject: FW: [oc] Translation
> >process
> >begin
> >
> >...
> >Wait on a;
> >
> >...
> >
> >wait on b;
> >
> >...
> >
> >wait on a;
> >
> >end;
> >
> Someone said me that even without a sensitivity list, the
> wait's must refer
> to a unique signal or port!
You mean in VHDL? No that is not true from a strict VHDL language/simulator standpoint. For Behavioral compiler it is the case that you should have all the waits waiting for the same kind of clock-edge.
Steven
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