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Message
From: Fernando Remus Nagel<frnagel@u...>
Date: Thu Jan 29 17:07:42 CET 2004
Subject: FW: [oc] Translation
At 06:02 29/01/2004, you wrote:> > My problem is that:
> >
> > My SC_CTHREAD have wait_until's of various signals/ports!
> >
> > It couldn't put wait_until's of different signals/ports in a
> > VHDL process!
> >
>
>
>You can do that. But you can't mix it with a sensitivity list. In SystemC
>you have the different wait's AND a sensitivity list. In VHDL it is either
>a sensitivity list OR waits in the process.
>E.g. the code below.
>
>process
>begin
>
>...
>Wait on a;
>
>...
>
>wait on b;
>
>...
>
>wait on a;
>
>end;
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
Someone said me that even without a sensitivity list, the wait's must refer
to a unique signal or port!
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