LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Fernando Remus Nagel<frnagel@u...>
    Date: Wed Jan 28 21:45:38 CET 2004
    Subject: FW: [oc] Translation
    Top
    > Hi,
    >
    > Here you find an extract out of the manual of Behavioral com
    piler from
    > Synopsys which shows you basically that SC_CTHREAD has been
    added to systemC
    > in order to be able to "reuse" behavioral compiler with syst
    emC.
    >
    >
    >
    > entity comp_mult is
    > port(
    > reset : in bit;
    > clk : in bit;
    > in_data : in integer range -128 to 127;
    > in_data_ready : in bit;
    > out_ready_for_data : out bit;
    > out_real : out integer range -32768 to 32767;
    > out_imag : out integer range -32768 to 32767);
    > end comp_mult;
    >
    > architecture behav of comp_mult is
    > begin
    > main_process : process
    > begin
    > reset_loop : loop
    > out_ready_for_data <= '1';
    > out_real <= 0;
    > out_imag <= 0;
    > wait until clk'event and clk = '1';
    > if (reset = '1') then exit reset_loop;
    > end if;
    > main_loop : loop
    > handshake_loop : while (in_data_ready = '0') loop
    > wait until clk'event and clk = '1';
    > if (reset = '1') then exit reset_loop;
    > end if;
    > end loop handshake_loop;
    > wait until clk'event and clk = '1';
    > if (reset = '1') then exit reset_loop;
    > end if;
    > out_ready_for_data <= '0';
    > wait until clk'event and clk = '1';
    > if (reset = '1') then exit reset_loop;
    > end if;
    > out_ready_for_data <= '1';
    > wait until clk'event and clk = '1';
    > if (reset = '1') then exit reset_loop;
    > end if;
    > end loop main_loop;
    > end loop reset_loop
    > end process main_process;
    > end behav;
    >
    > Redant Steven wrote:
    > >
    > > -----Original Message-----
    > > From: frnagel@u... [mailto:frnagel@u...]
    > > Sent: Wednesday, January 28, 2004 16:27
    > > To: cores@o...
    > > Subject: [oc] Translation
    > >
    > >
    > > How can I implement an SC_CTHREAD process in VHDL?
    > > _______________________________________________
    > > http://www.opencores.org/mailman/listinfo/cores
    >
    >
    > --
    >
    > Geert Vanwijnsberghe Project Engineer ASIC Design
    >
    > e-mail: vwb@i... IMEC, division INVOMEC
    > phone : +32 16 281 273 Kapeldreef 75
    > fax : +32 16 281 584 B-3001 Leuven, Belgium
    >
    > ------------------------------------------------------------
    -------------
    > This e-
    mail and/or its attachments may contain confidential informati
    on.
    > It is intended solely for the intended addressee
    (s). Any use of the
    > information contained herein by other persons is prohibited.
    IMEC vzw
    > does not accept any liability for the contents of this e-
    mail and/or its
    > attachments.
    > ------------------------------------------------------------
    -------------
    >
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores
    >
    I think that you don't understand my question! Or I your
    answer!
    How can I translate a SC_CTHREAD process to VHDL?


    --- Acabe com aquelas janelinhas que pulam na sua tela. AntiPop-up UOL - É grátis! http://antipopup.uol.com.br

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.