LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: nico at seul.org<nico@s...>
    Date: Wed Jan 28 17:49:41 CET 2004
    Subject: [oc] Potentially awesome open-source idea
    Top
    At we think about co-design.

    One of the opinion was to have a "tools" (software or/and langage) that
    could permit to write "executive spec" BUT reusing soon written IPs.

    The idea is to explore architecture as quickly as possible and reuse
    validated core (mainly peripherals).

    So IP modele could speed up simulation but model are never perfect or even
    exist.

    I don't know any tools that work that way. (a bunch of shell script, perl
    script, tcl script to control modelsim, + gcc compiler for the cpu model,
    + some asm to boot the cpu aren't consider as a tools :)



     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.