OPENCORES.ORG

Hi,
Here you find an extract out of the manual of Behavioral compiler from
Synopsys which shows you basically that SC_CTHREAD has been added to systemC
in order to be able to "reuse" behavioral compiler with systemC.

entity comp_mult is
port(
    reset : in bit;
    clk : in bit;
    in_data : in integer range -128 to 127;
    in_data_ready : in bit;
    out_ready_for_data : out bit;
    out_real : out integer range -32768 to 32767;
    out_imag : out integer range -32768 to 32767);
end comp_mult;

architecture behav of comp_mult is
begin
main_process : process
begin
   reset_loop : loop
     out_ready_for_data <= '1';
     out_real <= 0;
     out_imag <= 0;
     wait until clk'event and clk = '1';
     if (reset = '1') then exit reset_loop;
     end if;
     main_loop : loop
       handshake_loop : while (in_data_ready = '0') loop
         wait until clk'event and clk = '1';
         if (reset = '1') then exit reset_loop;
         end if;
       end loop handshake_loop;
       wait until clk'event and clk = '1';
       if (reset = '1') then exit reset_loop;
       end if;
       out_ready_for_data <= '0';
       wait until clk'event and clk = '1';
       if (reset = '1') then exit reset_loop;
       end if;
       out_ready_for_data <= '1';
       wait until clk'event and clk = '1';
       if (reset = '1') then exit reset_loop;
       end if;
     end loop main_loop;
   end loop reset_loop
end process main_process;
end behav;

Redant Steven wrote:
> 
> -----Original Message-----
> From: frnagel@u... [mailto:frnagel@u...]
> Sent: Wednesday, January 28, 2004 16:27
> To: cores@o...
> Subject: [oc] Translation
> 
> 
> How can I implement an SC_CTHREAD process in VHDL?
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores

-- 

Geert Vanwijnsberghe       Project Engineer ASIC Design

e-mail: vwb@i...        IMEC, division INVOMEC
phone : +32 16 281 273     Kapeldreef 75
fax   : +32 16 281 584     B-3001 Leuven, Belgium

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