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Message
From: bporcella<bporcella@s...>
Date: Wed Jan 28 17:34:10 CET 2004
Subject: [oc] Potentially awesome open-source idea
> -- Users post pre-synthesized cores to OpenCores (as well as RTL
> source), in a generic netlist format (this is something I know how to do).
> -- We write open-source tools that can combine those cores
> automatically, taking core-specific options, and running the author's
> customization scripts.
> -- This tool then spits out gate level Verilog/VHDL to the desired
> target (Xilinx, Altera, LSI, etc).
>
> The impact on design productivity is potentially huge.
>
> Any interest in discussing the idea?
>
> Bill
I don't have any basic problem with the idea - it seems relatively
straightforward to implement.
but don't see how impact on productivity could be potentially huge (or even
significant) -- unless of course the tool
also puts together the composite testbench and writes the total verification
suite.
bj
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