OPENCORES.ORG

Well how about having a web interface where you simply select the cores,

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On Wednesday 28 January 2004 22:23, Damjan Lampret wrote:
> Well how about having a web interface where you simply select the cores,
> set their addresses and interrupts (assuming this is a SoC with an embedded
> procsssor) and it gives you out the RTL of the SoC? This is something that
> will eventually (hoping for sooner than later) show up on opencores ;-)

Taking a page out of software development... and idea like this would require 
a lot of standardization.. especially interfacing... using WB itself is not 
sufficient.. for example, we would need the signals to be marked out clearly 
and specifically for interfacing.. even licensing would need to be 
standardized to avoid mix licenses used in an SoC..

it's an interesting idea.. but implementing it would require everyone's 
cooperation.. it would require OC to change it's role from a repository role 
(like SF, where anyone can dump anything) to something a little more like an 
organization that is charged with standardizing things, exporting API and 
maintaining a little more control over the things that get through (something 
more akin to KDE)..

But it would be great to see something like that... maybe a software similar 
to VB or Delphi, where we can drag and drop components onto a top level, link 
a few things together and click GENERATE and it'll dump out the final code.. 
then, we'll just need to do some optimizations.. and we've got ourself a 
complete SoC.. I wonder what would be the ramifications of that..

> regards,
> Damjan
>
> ----- Original Message -----
> From: "Rudolf Usselmann" <rudi@a...>
> To: "Discussion list about free open source IP cores" <cores@o...>
> Sent: Wednesday, January 28, 2004 3:10 PM
> Subject: Re: [oc] Potentially awesome open-source idea
>
> > On Wed, 2004-01-28 at 19:41, Bill Cox wrote:
> > > An idea just hit me that potentially could have a huge impact on the
> > > electronic design world.  I haven't thought about it enough to describe
> > > it clearly, or name it, so I'll just do a brain-dump of the components
> > > involved:
> > >
> > > -- Users post pre-synthesized cores to OpenCores (as well as RTL
> > > source), in a generic netlist format (this is something I know how to
>
> do).
>
> > > -- We write open-source tools that can combine those cores
> > > automatically, taking core-specific options, and running the author's
> > > customization scripts.
> > > -- This tool then spits out gate level Verilog/VHDL to the desired
> > > target (Xilinx, Altera, LSI, etc).
> >
> > We have actually talked about this way a while back !
> > We got stuck trying to determine how legal that would be
> > specially with tools like design compiler and may be even
> > Magma.
> >
> > > As an  example, an interactive (as well as batch) version of the tool
> > > takes inputs from the user, such as what CPU he wants, what
> > > peripherals, etc.  It then generates from generic gate-level source
> > > files a target specific netlist combining all the elements the user
> > > asked for, using wishbone, and any other good ideas we come up with.
> >
> > This sounds very interesting and probably also somewhat
> > difficult to implement. Perhaps we should provide a
> > environment for SoC building. One as a 'top end' with the
> > OpenRisc (32 bit) system, and one as a 'low end' with any
> > of the available 8 bit Micros.
> >
> > Perhaps this can be done with a perl script ?!
> >
> > > I think we can automate design reuse, and make if flexible enough to
> > > work with any combination of front-end and back-end tools.  The EDA
> > > industry wont do this (there are good reasons for this).
> >
> > Yes, I would definitely shoot for a source code instead of
> > a netlist generation.
> >
> > > The impact on design productivity is potentially huge.
> > >
> > > Any interest in discussing the idea?
> >
> > I'm definitely interested.
> >
> > My first input would be:
> >
> > 1) The authors of all the CPUs, must write a Wishbone
> >     Interface wrapper for their CPU. Or perhaps some other
> >     volunteer.
> > 2) The authors of peripheral IP must provide a Wishbone
> >     wrapper for their peripheral/device IP.
> > 3) I would volunteer to take it all and put it together in
> >     to one huge (low end) SoC. Perhaps someone from Damjans
> >     group could provide a 'high end' version ?!
> >
> > > Bill
> >
> > Cheers,
> > rudi
> > ========================================================
> >    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> > ..............::: FPGAs * Full Custom ICs * IP Cores :::
> > FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools
> >
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/cores
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores

- -- 
with metta,
Shawn Tan.

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-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.3 (GNU/Linux)

iD8DBQFAF95s9KUEj/m6O5oRAuxeAJ9a74B/C4sQvYufHaFehwvxJC3guwCcDU5p
BCrsrTrowpDeetWNJN+H5cs=
=FEXo
-----END PGP SIGNATURE-----