OPENCORES.ORG

On Wed, 2004-01-28 at 19:41, Bill Cox wrote:

Well how about having a web interface where you simply select the cores, set
their addresses and interrupts (assuming this is a SoC with an embedded
procsssor) and it gives you out the RTL of the SoC? This is something that
will eventually (hoping for sooner than later) show up on opencores ;-)

regards,
Damjan

----- Original Message ----- 
From: "Rudolf Usselmann" <rudi@a...>
To: "Discussion list about free open source IP cores" <cores@o...>
Sent: Wednesday, January 28, 2004 3:10 PM
Subject: Re: [oc] Potentially awesome open-source idea

> On Wed, 2004-01-28 at 19:41, Bill Cox wrote:
> > An idea just hit me that potentially could have a huge impact on the
> > electronic design world.  I haven't thought about it enough to describe
> > it clearly, or name it, so I'll just do a brain-dump of the components
> > involved:
> >
> > -- Users post pre-synthesized cores to OpenCores (as well as RTL
> > source), in a generic netlist format (this is something I know how to
do).
> > -- We write open-source tools that can combine those cores
> > automatically, taking core-specific options, and running the author's
> > customization scripts.
> > -- This tool then spits out gate level Verilog/VHDL to the desired
> > target (Xilinx, Altera, LSI, etc).
>
> We have actually talked about this way a while back !
> We got stuck trying to determine how legal that would be
> specially with tools like design compiler and may be even
> Magma.
>
> > As an  example, an interactive (as well as batch) version of the tool
> > takes inputs from the user, such as what CPU he wants, what peripherals,
> > etc.  It then generates from generic gate-level source files a target
> > specific netlist combining all the elements the user asked for, using
> > wishbone, and any other good ideas we come up with.
>
> This sounds very interesting and probably also somewhat
> difficult to implement. Perhaps we should provide a
> environment for SoC building. One as a 'top end' with the
> OpenRisc (32 bit) system, and one as a 'low end' with any
> of the available 8 bit Micros.
>
> Perhaps this can be done with a perl script ?!
>
> > I think we can automate design reuse, and make if flexible enough to
> > work with any combination of front-end and back-end tools.  The EDA
> > industry wont do this (there are good reasons for this).
>
> Yes, I would definitely shoot for a source code instead of
> a netlist generation.
>
> > The impact on design productivity is potentially huge.
> >
> > Any interest in discussing the idea?
>
>
> I'm definitely interested.
>
> My first input would be:
>
> 1) The authors of all the CPUs, must write a Wishbone
>     Interface wrapper for their CPU. Or perhaps some other
>     volunteer.
> 2) The authors of peripheral IP must provide a Wishbone
>     wrapper for their peripheral/device IP.
> 3) I would volunteer to take it all and put it together in
>     to one huge (low end) SoC. Perhaps someone from Damjans
>     group could provide a 'high end' version ?!
>
> > Bill
>
> Cheers,
> rudi
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