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Message
From: Bill Cox<bill@v...>
Date: Wed Jan 28 13:41:11 CET 2004
Subject: [oc] Potentially awesome open-source idea
An idea just hit me that potentially could have a huge impact on the
electronic design world. I haven't thought about it enough to describe
it clearly, or name it, so I'll just do a brain-dump of the components
involved:
-- Users post pre-synthesized cores to OpenCores (as well as RTL
source), in a generic netlist format (this is something I know how to do).
-- We write open-source tools that can combine those cores
automatically, taking core-specific options, and running the author's
customization scripts.
-- This tool then spits out gate level Verilog/VHDL to the desired
target (Xilinx, Altera, LSI, etc).
As an example, an interactive (as well as batch) version of the tool
takes inputs from the user, such as what CPU he wants, what peripherals,
etc. It then generates from generic gate-level source files a target
specific netlist combining all the elements the user asked for, using
wishbone, and any other good ideas we come up with.
I think we can automate design reuse, and make if flexible enough to
work with any combination of front-end and back-end tools. The EDA
industry wont do this (there are good reasons for this).
The impact on design productivity is potentially huge.
Any interest in discussing the idea?
Bill
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