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Message
From: Richard Herveille<richard@a...>
Date: Thu Jan 22 08:24:37 CET 2004
Subject: [oc] Wishbone Addressing
The SEL lines signal on what byte(s) (if you’re using 8bit
fragmentation) data is expected (read operation) or on what byte(s)
valid data is present (during a write operation).
For a read operation on a 32bit databus you can always output the entire
qword; simply ignoring the SEL bits, because the correct data is always
present on the correct byte(s). The other bytes are defined to contain
invalid data, so it is perfectly legal to output the entire 32bit
dataword.
For a write operation you need to mask your internal write signal with
the SEL lines of course.
Now as for the code-piece below, I don’t know what the authors intend
with it. But simply outputting the correct register would have done the
trick as well. Nor does it make sense to add an enable (re_o) to the
wb_dat_o registers. Always output data, even during a write operation,
the external bus arbiter (e.g. CONMAX IP core) takes care of routing the
correct data.
Just my 2cents, the original authors should comment on it as they
understand what they intend to build.
Richard
Hi All:
My first posting. I've been mucking around with the UART
core attachment.htm
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