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Message
From: gupg at yahoo.com<gupg@y...>
Date: Sun Dec 28 19:45:26 CET 2003
Subject: [oc] SystemC design flow
Fabrizio
Did you do any analysis of the SPARK tool ? We are also trying to
evaluate this tool and are trying to figure out if it is even good for
C models - converting synthesizable SystemC to C should not be that
hard. Also, the SPARK tool guys are planning to provide SystemC
support in the future.
What was your analysis of the SPARK tool ?
GG
----- Original Message -----
From: Fabrizio Fazzino <fabrizio@f... >
To: cores@o...
Date: Sun, 28 Dec 2003 17:38:24 +0100
Subject: [oc] SystemC design flow
>
>
> Hi guys,
> I'd like to know if there is some possibility to build
> up a design flow starting from a synthetizable SystemC
> source, and without the need of using a Synopsys license.
>
> AFAIK the only synthesis tool that accepts SystemC as
> an input (following the rules stated in the "Describing
> Synthesizable RTL in SystemC" document available from
> Synopsys) is Behavioral Compiler (still from Synopsys),
> but I suspect that its license fee is quite expensive for
> non-commercial purposes.
>
> BTW, some time ago an academic version of BC was freely
> downloadable from Synopsys web site, but I can't find it
> anymore.
>
> Days ago I've found a post from Sumit Gupta about a tool
> called SPARK that lets you transform ANSI C into VHDL, but
> I had a look and I didn't like it so much; a converter
> from SystemC to VHDL should be very useful because I
> should be able to convert from SystemC to VHDL and then
> to synthetize the VHDL using an open tool like Alliance.
>
> Thank you in advance for your suggestions,
> Fabrizio
>
> --
> =============================================
> Fabrizio Fazzino, IT Engineer
> fabrizio@f... - http://www.fazzino.it
> =============================================
>
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